Abstract

The architecture and components of the SDH network layers responsible for synchronisation are currently being proposed by the European Telecommunications Standards Institute (ETSI). To aid the standards process a general model has been proposed of the noise generated by individual clock elements. It can be shown that this model can be interpreted as a certain type of phaselock loop. This model has been implemented using the simulation tool Signal Processing Workstation and extended to more accurately reflect the characteristics of SDH synchronisation clocks. It was found that as well as there being a fundamental contradiction as to the use of the model, one major block has been incorrectly specified. New values have been obtained for parameters in the model so that clocks satisfy the individual standards for noise generation. It has been verified that in a reasonable worst case synchronisation network topology, such clocks satisfy the standards for the production of low frequency phase offsets known as wander. 1.5