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Simulating the Wander Accumulation
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Acknowledgements
Contents
Abstract
Acknowledgements
Contents
List of Figures
Introduction
Project Aims
The Need for Synchronisation
Structure of Thesis
Summary of Main Contributions
The ETSI Standard detailing the Generic Requirements of SDH Synchronisation Networks
Clock Types
Modes of Operation
Synchronisation Network Architecture
Inter-node Distribution Architecture
Intra-node Distribution Architecture
The Synchronisation Network Reference Chain
The Masks Defined in the ETSI Standards
Wander Masks for individual clocks
PRC Wander Masks
SSU Wander Masks
SEC Wander Masks
Synchronisation Reference Chain Masks
Wander Limits at PRC Outputs
Wander Limits at SSU Outputs
Wander Limits at SEC Outputs
Wander Limits at PDH Outputs
The ETSI Synchronisation Clock Noise Model
Bandwidths of the various clock types
A Contradiction: Setting the Gain Values
Anti-aliasing and Simulation Time
Summary
Noise Theory and Phaselock Loops
Frequency Metrology Measures
Basic Definitions
Relationship between Phase and Frequency Fluctuations
Classification of Noise Types present in a Clock
Flicker Phase Noise Shaping of Filter A
Phaselock Loops
Basic PLL Components
Analysis of basic PLL Function
Filter Transfer Functions and Loop Orders
Second Order PLL's
Performance Comparison of Different Loop Orders
Noise Rejection Performance
PLL Tracking
Tracking phase steps
Tracking Frequency Steps
Achieving Simultaneous Tracking and Noise Rejection Performance
Summary
Time Stability Quantities
Selection of TDEV as a performance measure
Rationale Behind TDEV
TDEV as a function of fractional frequency error
TDEV as a function of Time Error
TDEV in terms of power spectral density
An approximate expression for TDEV illustrating its filtering behaviour
TDEV Response to Different Noise Types
Continuous TDEV
MTIE
Summary
Relationship between ETSI and PLL Noise Models
Power Spectral Densities of Noise Sources in ETSI Model
PLL Noise Model
One Possible Interpretation of the ETSI Noise Model
Validity of Model Assumptions
Suggested Model Improvements
Applying the ETSI Model to Primary Reference Clocks
Extending the ETSI Clock Noise Model
Summary
Theoretical Analysis of the TDEV Produced by the ETSI Noise Model
TDEV approximations for the two Branches of the Noise Model
TDEV Generated by the Top Branch of the Noise Model
TDEV Generated by the bottom branch of the noise Model
Bounds on the TDEV Produced by the Model
Limiting Values of TDEV of Top Branch of Model
Limiting Values of TDEV of Bottom Branch of Model
Approximating TDEV at the model output
Comparison with Published Approximations
The shape of the TDEV Wander Masks
Problems with the SEC TDEV Wander Mask
Experimental Results Substantiating the Model Assumptions
Summary
Implementing the Model
Basic Model of One Clock
Modelling Flicker Phase Filter A
Implementing the 5Hz Noise Bandwidth
Reducing the File Size and Simulation Time
Reducing the Simulation time for TDEV
Reducing the Simulation time for MTIE
Extending the Model
Simulating a Maximum Reference Chain
Post Processing to Obtain TDEV and MTIE data
Calculating TDEV
Calculating MTIE
Summary
Results
Results of Simulating the Individual Clock Models
The SSU Noise Model
The SEC Model
The SEC Model for Parameters Proposed in ETSI Part 5
The PRC Model
Simulating a Maximum Reference Chain
Noise Filtering Characteristic of a SSU
Verifying the Correct Simulation of Filter A
Evidence of a problem
Testing Filter A
Theoretical Analysis of the TDEV behaviour of WGN shaped by filter A
Results
Graphical Analysis of the filter A transfer function
Suggested Modification to Filter A
The use of SPW Interpolate Blocks
The effect of decimating on TDEV data
The effect of decimating data on MTIE results
Summary
Conclusions
Summary of Contributions
Suggestions for Future Work
Correspondence with Dominico De Seta
Source Code
TDEV Program Source Code
MTIE Source Code
References
Mark J Ivens
11/13/1997