The ETSI Synchronisation Clock Noise Model

 

 

Figure 2.21:   General model of the noise generated by a SDH synchronisation clock

The ETSI noise model that was implemented on SPW will now be outlined. The following model takes the two most important sources of noise, white phase modulation and flicker phase modulation and models them separately. The model outputs the time error x(t) as defined in equation (3.2).

The noise sources generate Gaussian white noise with zero mean, a standard deviation $\sigma=1ns$ and a noise bandwidth of B_n=5Hz.

The transfer functions of the three filters are as follows. Filter A models flicker phase noise spectral shaping:  

$$H_A(s)=\prod_{n=1}^8{\frac{1}{\sqrt{7}}\cdot\frac{s+\sqrt{7}\alpha_n}{s+\alpha_ n}}$$ (1)

where $\alpha_{n+1}=7\alpha_n$ and $\alpha_8=2\pi \cdot 6.72 rad/s$.
Filter A is a half-order integrator as the transfer function for filter A, (2.1) can be approximated by  

$$H_{A}(s)\approx \frac{ \sqrt{2 \pi f_0}}{s^{\frac{1}{2}}} \q... ...here} f_{0}=\frac{\alpha_{1}}{2 \pi \sqrt[4]{7}}\approx 5\mu Hz$$ (2)

Filters B and C take into account the filtering action of the loop while the clock is locked to its reference input. Filter B models the low pass filtering of the noise due to the phase detector and loop filter of a PLL of bandwidth B.  

$$H_B(s)=\frac{\beta}{s+\beta} \qquad \beta = 2 \pi \cdot B$$ (3)

Filter C models the high pass filtering of the phase noise due to the voltage controlled oscillator of a PLL of bandwidth B.  

$$H_C(s)=\frac{s}{s+\beta} \qquad \beta = 2 \pi \cdot B$$ (4)