Introduction

 Transmission equipment based on the plesiochronous digital hierarchy (PDH) does not require synchronisation since bit stuffing allows the multiplexing of asynchronous sources with substantial frequency variations. However, the transmission standard SDH requires that all of the elements making up the network are highly synchronised. Poor quality synchronisation in SDH results in a process known as a pointer adjustment which is to be avoided. Also, in order to minimise the end to end data delay in an SDH transport network, and prevent slip due to buffer overflow and emptying, a high degree of synchronisation is required. This is achieved by a synchronisation signal being generated and subsequently selected, regenerated and then propagated by a chain of clocks. The attributes of each of the clock types as well as the maximum length of the synchronisation path are currently being finalised by the European Telecommunications Standards Institute (ETSI) [1]-[6]. Although the standards are necessarily implementation independent, one possible clock implementation utilises a phaselock loop. A general model of the noise generated by a synchronisation clock has also been proposed which can be related to the noise performance of a phaselock loop.

Work has been carried out to simulate the noise generated by each of the clock types. This has allowed the validity of the proposed model to be examined. The successful simulation of each clock type has allowed the noise generated by the maximum chain of clocks to be simulated and the effect that changing performance characteristics of the clocks would have on the noise at the end of the clock chain to be examined. Modelling was carried out by utilising the simulation package Signal Processing Workstation (SPW). Post processing of data to generate the required statistical measures was performed by code written in C.