The Need for Synchronisation

Synchronisation Networks were originally deployed to exploit digital time switching. The Plesiochronous Digital Hierarchy (PDH) does not itself require synchronisation but is used to supply timing to switching nodes. PDH synchronisation is achieved via mechanisms such as line coding and bit-stuffing. Because SDH has differing synchronisation requirements, care must be taken in the design of synchronisation components especially as backwards compatibility with PDH must be achieved. The large installed base of 64kbit/s digital switches will tolerate a certain level of differential wander before controlled slip occurs and therefore synchronisation network wander has to be kept to a level that is compatible with the 64kbit/s switched network.

A high speed synchronous network is fundamental to the efficient and flexible transport of broadband services. This is because future broadband networks must support differing bandwidths for different services and therefore the switching rates will be different within the same switch fabric. A fully synchronous hierarchy is needed so that narrow band and wide band services can co-exist on the same network. In order to exploit cost efficient time switching components, the identity of channels at all levels in the transmission hierarchy must be completely determined by the position of the channels in the frame. So the multiplexing scheme must be truly synchronous throughout the network with a single master clock defining the slot intervals and that all frames will be constructed by interleaving at rates derived from this single clock, with all frames aligned.

SDH can easily cope with large phase shifts when transporting containers through network elements but in order to restore the original signal, such shifts have to be smoothed out to below a tolerable limit. Phase fluctuations can be classified as jitter if their signal spectrum exceeds a limit frequency (20Hz at 2.048Mbit/s, for example) and wander if the fluctuations lie below the limit frequency. In order to keep jitter and wander tolerable, pointer actions of the same polarity must be separated by sufficient time intervals.

The process of evolution from PDH to SDH transport networks place extra demands on the synchronisation architecture. When a PDH signal is carried over SDH, it is first mapped into SDH bytes by a synchroniser element. These bytes are subsequently mapped into the payload of a virtual container (VC). Bit justification is used in the mapping process to match the plesiochronous tributary frequency variations to that of the mapper node. Byte justification is utilised during the SDH transmission process when frequency mismatches occur between the clocks in pointer processors. At the end of the transmission process the PDH signal is reconstructed at a data rate as close to the original as possible. Thus asynchronous mapping is used to map SDH data into PDH networks. Data traversing several PDH and SDH networks places the greatest demand on synchronisation quality.

The pointer mechanism leads to strenuous demands on the stability of clocks in SDH networks. Because the quantisation threshold is 1 or 3 bytes (rather than 1 bit for PDH) the phase noise caused by a pointer adjustment is rather large. Also it is reported [27] that pointer adjustment phase transients have significant low frequency (<1Hz) components which are difficult to filter out. These problems necessitate keeping pointer adjustments to a minimum. Since pointer processors are highly sensitive to short term degradations in stability, node clocks are required to have high short term phase stability. In order to provide this, a synchronisation network is being defined.

It will be seen that individual clocks essentially low pass filter noise on their inputs. Thus high frequency jitter caused by PDH justification and other effects does not generally cause excessive problems in terms of SDH synchronisation. Rather, it is the low frequency wander that is produced because of basic clock noise then passed transparently by successive clocks until it is absorbed by terminating slip buffers that is an issue. For example, the International Telecommunications Union has specified that receiving slip-buffers should experience a maximum input wander of $18\mu s$ over 24 hours. Excessive wander can cause the buffers to eventually fill up or empty, causing a frame to be lost or repeated (frame slip). It is therefore important to put a limit on the wander caused by clock noise. This requires the effect that clock attributes have on synchronisation network performance and wander accumulation in particular to be understood.