Reducing the Simulation time for TDEV

 As previously discussed, the ETSI standards [3] and [4] require a simulation time, T of at least 12 times the largest observation interval being measured at a sampling interval of at least 30Hz i.e.

In order to simulate a Primary Reference Clock which has a wander mask defined for observation intervals up to 10,000s [6], this required the generation of 600 hours of simulation data at a sampling frequency of 30Hz. As well as putting a considerable strain on computer storage facilities, the time taken to produce TDEV data from such a file is inordinately long. Despite the prescribed 30Hz minimum sampling interval, it was decided to attempt to utilise the SPW decimate block in order to reduce the size of the file produced by SPW. Simulations were performed for clocks with and without the addition of a decimate block immediately before the signal sink. From the results presented in section 8.5, it was determined that it was possible to decimate the output file to produce TDEV data for observation intervals $\tau\geq 10^1s$. It was appropriate to use un-decimated data for observation intervals smaller than 1 second but this placed minimal demands on processing time and file storage and so was a satisfactory outcome. Since it will be seen in section 7.2.2 that time error data was collected at a sampling frequency of 30Hz, MTIE time error data was also used to calculate TDEV for $\tau\leq10s$.

The SPW block diagram for the collection of time error data for the calculation of TDEV for one clock (in this case a Synchronisation Supply Unit) is shown in figure 7.6. the block for one Synchronisation Supply Unit is located in the left of the figure and it encapsulates the SSU model which is of a similar form as shown in figure 7.3.

 

Figure 7.6:   SPW block diagram of system for collecting data for SSU TDEV calculation

The low pass filter in the diagram carries out anti-aliasing is a first order order Butterworth with a 30Hz sampling frequency, 0.2dB passband ripple and a 10Hz passband edge so as to satisfy the standards as described in section 2.4.3. The two signal source blocks provide sampling frequency signals. The bottom left block outputs a 30Hz sampling frequency which is propagated to the individual clock block. The bottom right signal source block provides the sampling frequency for the signal sink which because of the use of the interpolate block, runs at 3 rather than 30Hz.