Basic PLL Components

 The material in this section is adapted from [11]. The basic function of a phaselock loop, in the context of this work, is to maintain the frequency of an oscillator exactly equal to the average frequency of an input signal. This function lends itself to be utilised in SDH synchronisation clocks. A phaselock loop consists of three basic components as shown in figure 3.1.

 

Figure 3.1:   Basic PLL block schematic

These three components are:

• A Phase Detector (PD)
• A loop filter
• A Voltage Controlled Oscillator (VCO) whose frequency is controlled by an external voltage

The function of these three components is as follows. The phase detector compares the phase of the input signal with the VCO phase and outputs a measure of the phase difference. This difference voltage is subsequently filtered by the loop filter and passed to the VCO. This control voltage changes the frequency of the VCO so as to reduce the phase difference between the oscillator and the input signal. When the loop is locked the frequency of the VCO is equal to the average frequency of the input signal. The behaviour of the various components and definitions of the constants in figure 3.1 is discussed in section 3.4.2.

Loop operation can also be thought of in a slightly different manner which aids in the logical connection between a phaselock loop and an SDH synchronisation clock. If one considers that the incoming signal to a phaselock loop contains additive noise, the loop reproduces the original signal by removing as much noise as possible. Thus one may think a phaselock loop as a kind of filter that passes a signal and rejects noise. The two important characteristics of this filtering behaviour of a phaselock loop are small bandwidth in order to reject large amounts of noise and the ability of the filter to automatically track the signal frequency.