Phaselock Loops

As described in section 2.1 the main functions of Synchronisation Supply Units and SDH Equipment Clocks are to synchronise their internal clocks with an input synchronisation signal and to reproduce the synchronisation signal after the removal of any additive noise components. One possible implementation of this basic clock function is by use of a phaselock loop. Although it is not seen to be the place of the European Telecommunications Standards Institute to recommend any particular implementation of clock, it will be seen that the ETSI model can be thought of as modelling a particular type of phaselock loop. For this reason, and to aid the understanding of theory presented in later chapters, some phaselock loop theory is discussed in the following sections.