The Synchronisation Network Reference Chain

 In this section the synchronisation reference chain will be discussed with reference to the definitions in [2] and [3]. As the number of clocks linked in tandem increases a synchronisation signal is increasingly degraded. To maintain quality of synchronisation, it is therefore important to specify a limit to the extent to which clocks may be cascaded as well as setting a limit on the degradation of the synchronisation signal. Such a reference chain is shown in figure 2.3. It is this synchronisation reference chain that has been simulated.

 

Figure:   The Synchronisation Network Reference Chain after [2]

As shown in the diagram, the reference chain consists of K Synchronisation Supply Units, each linked by N SDH equipment clocks. The values of K and N have been provisionally set [2] at K=10 and N=20 with the provision that the total number of SDH Equipment Clocks is limited to 60. However, operators may use different number of clocks as long as the network limits for jitter and wander are satisfied.

The standards [3] specify the maximum jitter and wander at four points in the synchronisation reference chain. These locations are shown in figure 2.4.

 

Figure:   The network limits in the synchronisation reference chain after [3]

As well as limits at the outputs of PRC's SEC's and SSU's, an additional network limit has been specified. Synchronisation may be delivered via a 2Mbit/s PDH path traversing several PDH line systems and multiplexing stages. This leads to a fourth network limit. These limits are detailed in section 2.3.2. The reference chain has to take into account the transitional period in which synchronisation paths traverse both SDH and PDH networks. An incoming PDH signal is mapped into SDH bytes by a synchroniser in a mapper node using bit justification. The SDH bytes are then mapped into the payload of a virtual container and transmitted. Delays in the SDH network will result in byte justification and pointer adjustment. At the end of the SDH network they are converted into a PDH bitstream at a data rate as close as possible to the original. The combination of a synchroniser, multiple pointer processors and a desynchronisers is collectively known as an SDH island . Any bit stuffing and pointer adjustments experienced by the data cause phase discontinuities that need to be reduced to a level that is acceptable for digital switching. Until legacy equipment is replaced, data may span several PDH networks and this places the most demands on the synchronisation network. Jitter and wander accumulation will peak when there are an equal number of PDH and SDH islands with a large number of pointer processors. In order to derive network jitter and wander limits, a `reasonable worst case' network model was defined [3]. Such a network is illustrated in figure 2.5 taken from [3].

 

Figure:   Wander accumulation across SDH islands from [3]

It was decided that there should be 4 SDH islands, each island consisting of 8 TU-12 pointer processors. Each island is timed from a separate synchronisation reference chain.