Experimental Results Substantiating the Model Assumptions

 In section 5.3.1 it was stated that discussion as to the validity of the assumptions as to the type and location of the noise sources in the ETSI model would be presented in a later section after additional theory had been presented. The discussions on TDEV masks in this allow such a discussion to follow. The reader is referred to the PLL transfer functions (5.11), (5.12) in order to appreciate the material in this section. Figure 6.4 after Carbonelli et al. [26] shows the experimental results of TDEV obtained on a reference output of an ADM-1 containing a clock with bandwidth of $B\approx20mHz$.

 

Figure:   Experimental TDEV data for an SEC from [26]

One simple argument is that the results presented in chapter 8 show that the model produces similar behaviour to that in figure 6.4. It can also be seen that at observation intervals $\tau\leq0.2s$ a white phase noise component is present as the slope is approximately $-\frac{1}{2}$. Consider once again the transfer functions (5.11) (5.12) between points A and B in figure 6.5 as well as the PLL transfer function (3.13).

 

Figure 6.5:   PLL Block schematic

As short observation intervals correspond to high frequencies, and a phaselock loop low pass filters noise at the input and at the phase detector output, it may be argued that white noise is being injected at the VCO output where from the above expression for H_A(s), the noise is essentially high pass filtered. Similarly, the (somewhat tenuous) flat TDEV behaviour indicative of $\frac{1}{f}$ flicker phase noise at large observation intervals leads to the assumption that such a noise source is being injected at a point in the PLL where it is being low pass filtered.