Validity of Model Assumptions

 From the discussion in section 3.4.4, it can be seen that first-order PLL implementations are uncommon because of poor performance. It is believed that the loop filter has been neglected for the sake of simplicity. Since it has been argued that the standards and hence the model should independent of any particular implementation, it was decided by ETSI that a model more accurately reflecting the properties of phaselock loops would be inappropriate.

Substituting $\sigma=10^-9$s, B_n=5Hz as defined in section 2.4 and taking $K_d\sim1$ in equation (5.17) results in  

$$c\sim 10^{-19}K_f^2.$$ (45)

Performing a similar process to (5.19) gives the expression  

$$k\sim 10^{-19}K_w^2$$ (46)

Brugia et al. [9] after Kroupa [8] quote the following expressions for the power spectral density of phase noise produced by a typical 5MHz crystal oscillator used in telecommunications applications

Hence substituting c=10^-13 into (5.21), it may be seen that a suitable value of K_f corresponding to a typical PLL is of the order

$$K_f\sim10^3.$$ (47)

Performing a similar process by substituting k=10^-15.5 into (5.22), results in the expression

$$K_w\sim10^{1.75}.$$ (48)

From the bounds on K_f and K_w proposed in the standards (K_f=O(10³), K_w=O(10⁰)) ([14], [4] and section 2.4.2), it can be seen that the bound on K_w puts strenuous limits on the VCO noise and that the bound on K_f is readily achievable by typical phase detectors and loop filters.

The argument as to only assuming flicker phase noise at the phase detector output/loop filter input and white phase noise at the VCO output is somewhat tenuous. Further theory is needed to be presented to enable discussion of this and the reader is thus referred to section 6.5.