Summary

In this chapter, the ETSI standards relevant to the problem at hand have been presented. The synchronisation network architecture as well as the individual clock types have been discussed. The concept of the maximum synchronisation reference chain has been introduced. The prescribed bounds on the clock bandwidths have been presented and the measures of clock performance, known as wander masks have been detailed. The reader has been presented with the clock model that has been simulated as well as guidelines on how the results are to be collected. Also, a contradiction in the current draft of the standards documents has been highlighted.

The next chapter presents theory necessary to subsequently derive the noise model presented in this chapter. It discusses some frequency metrology concepts which are required in order to define the data that is produced by the model and in order to gain insight into some of the concepts involved in measuring the frequency characteristics of clocks. A general theory of phaselock loops is presented so that a link between the model and phaselock loops may be subsequently derived.